Research

Graduate Research (The University of Texas at Austin)
Design of Energy-Efficient Circuit/Architecture for AlexNet CNN (October’18 – February’20)

Mentor:  Prof. Jaydeep Kulkarni , Assistant Professor, ECE Dept., The University of Texas at Austin.

  • Taped out second test-chip in 65nm CMOS node implementing energy efficient signed 8-bit input/weight MAC operations for AlexNet CNN.
  • Proposed and Implemented compressed time-domain CNN approach resulting in ≥ 60% improvement in throughput.
  • Proposed approach is scalable to higher bit-widths with novel time residual multiplication approach with minimal circuit overhead.
  • Proposed and Implemented Partial Convolution Compute technique – leads to 15%-25% reduction in number of MACs in AlexNet for <1% drop in accuracy.
  • Proposed novel data storage and access techniques to reduce on-chip memory access savings by 20% compared to state-of-the-art techniques.
Design of Time-Domain Energy-Efficient Circuit for LeNet-5 CNN (January’18 – October’18)

Mentor:  Prof. Jaydeep Kulkarni , Assistant Professor, ECE Dept., The University of Texas at Austin.

  • Demonstrated an energy-efficient Convolutional Neural Network (CNN) engine by performing Multiply and Accumulate (MAC) operations in the time domain.
  • The time-domain CNN engine employs a novel bi-directional Memory Delay Line (MDL) unit to perform signed accumulation of input and weight products. The proposed MDL design leverages standard digital circuits and doesn’t require any capacitors, complex analog-to-digital converters to realize convolution operation enabling easy scaling across the process technology nodes.
  • The proposed time domain MDL design implements a LeNet-5 CNN engine in a commercial 40nm CMOS process achieving energy efficiency of 12.08 TOPS/W, throughput of 0.365 GOPS at 537mV in 16x speed-up mode, while achieving 98.42% classification accuracy.
  • Furthermore, two methods of scaling MDL’s to multi-bit weights are proposed.
  • The proposed MDL based time-domain approach performing 1-bit/8- bit weight and 8-bit input MAC operations when compared with the corresponding baseline digital implementations show 2.09x- 2.32x higher energy efficiency and 2.22x-3.45x smaller area.
  • This work has been published in IEEE JSSC journal, and IEEE ISSCC and DAC conferences.
Design Methodology for High-Mix, Low-Volume, Heterogeneously Integrated Designs (June’17 – June’19)

Mentors:  (1) Prof. S.V. Sreenivasan, Professor, ECE Dept. and ME Dept. (2) Prof. Jaydeep Kulkarni , Asst. Professor, ECE Dept. (3) Prof. Mark McDermott, Adjunct Faculty and EIR, ECE Dept., The University of Texas at Austin.

  • Proposed EDA methodology that enables sharing of the mask cost for the front-end nano-scale feature sizes across many ASICs. This work has been accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; details to be disclosed soon.
Masters Thesis – EDA Design for Low-Volume High-Mix ASICs (June’16 – May’17)

Mentors:  (1) Prof. S.V. Sreenivasan, Professor, ECE Dept. and ME Dept., The University of Texas at Austin. (2) Prof. Mark McDermott, Adjunct Faculty and EIR, ECE Dept., The University of Texas at Austin.

  • This technology is a novel application of the high-speed, precision assembly technique for fabrication of ASICs using a limited number of mass-produced feedstock (micro-scale) logic circuits.
  • Developed EDA methodology and algorithms for optimal feedstock design, generation of feedstock preplaced design, generation of design collaterals to support EDA flow, and front end synthesis flow to meet the required functionality of design and achieve optimal quality of results (QoR) metrics in terms of circuit performance/speed, power and area.
UVM and Formal Verification of AES Module (March’17 – May’17)

Mentor: Prof. Jacob Abraham, Professor, Department of Electrical and Computer Engineering, The University of Texas at Austin.

  • Implemented UVM and Formal Verification techniques to verify Advanced Encryption Standard (AES) module.
  • Emphasis on improving code and functional coverage in UVM,  assertions developed to test functionality of state machines for all sub-modules of AES block. [View: PDF (Presentation)]
A Fast and Efficient Algorithm for FPGA Detailed Placement (Oct’16 – Dec’16)

Mentor: Prof. David Pan, Professor, Department of Electrical and Computer Engineering, The University of Texas at Austin.

  • Proposed and Implemented 2 heuristics based detailed placement algorithms for FPGA placement, along with implementation of greedy apporach algorithm.
  • Provided different optimization modes to address runtime vs performance tradeoff, achieved scalable runtimes for complex benchmarks [View: PDF (Paper)  PDF (Presentation)]
Design of a high performance 800MHz  dual Amber core processor (Feb’16 – May’16)

Mentor: Prof. Mark McDermott, Adjunct Faculty Member, Department of Electrical and Computer Engineering, The University of Texas at Austin.

  • Synthesis, floorplanning, powerplanning, PNR, ECO, formal verification, timing and power signoff of 800 MHz dual amber core processor.
  • All the specifications (timing, power and placement utilization) are met with good margin. [View: PDF]
Design of a low power, low noise gm-boosted current reuse LNA with passive voltage-mode mixer receiver (Feb’16 – May’16)

Mentor: Prof. Ranjit Gharpurey, Professor, Department of Electrical and Computer Engineering, The University of Texas at Austin.

  • Designing and Simulation of a low power, low noise gm-boosted current reuse LNA with passive voltage-mode mixer receiver.
  • All the specifications are met with good margin keeping in mind design trade-offs to optimize for power. [View: PDF]
Design of a telescopic fully-differential OTA (Oct’15 – Dec’15)

Mentor: Prof. Nan Sun, Assistant Professor, Department of Electrical and Computer Engineering, The University of Texas at Austin.

  • Designing and Simulation of a low power, noise high performance two-stage telescopic fully-differential OTA with CMFB loop.
  • All the specifications are met with good margin keeping in mind design trade-offs to optimize for power. [View: PDF] [View: Powerpoint]
Design of 12 lead Clinical ECG Measuring System (Oct’15 – Dec’15)

Mentor: Prof. John Pearce, Professor, Department of Electrical and Computer Engineering, The University of Texas at Austin.

  • Designing of a 12 lead Clinical ECG measuring system using industry components (Opamps, INA, T/F, Fuse, ADC, ISO, etc)
  • Design tradeoffs are considered to optimize for performance, cost, power and noise. [View: PDF]
Design of ALU and SRAM Layout (Aug’15 – Oct’15)

Mentor: Prof. Jacob Abraham, Professor, Department of Electrical and Computer Engineering, The University of Texas at Austin.

  • Designed 16 bit ALU  for shift (arithmetic, logic, rotate), logic, comparator, and arithmetic (signed and unsigned) operations.
  • Implemented layout of 1-bit SRAM cell in Cadence with optimization techniques to save area.

 

Research at Qualcomm
A Versatile Modulator-Filter Topology for AFE Designs, Qualcomm (October’13 – March’14)

Mentor: Venu Pakalapaty, Senior Staff Manager, Qualcomm India Pvt. Ltd.

  • The novel idea implements designing of a versatile cell which does efficient merging of both Modulation (Sigma Delta, Delta, FM and AM) and Filtering (Highpass, Lowpass, All pass, Bandpass) which gives phenomenal results in terms Power and Area.  The feature set is still intact when compared to existing products out in market, but at improved QOR.
  • Filed an Invention Disclosure Form (IDF) for Patent Application in RF patent review board. (Currently working on detectability aspects).
Dynamic Standard Cell Library Generation, Qualcomm (January’14 – May’14)

Mentor: Shankar Nagarajan, Senior Staff Manager, Qualcomm India Pvt. Ltd.

  • The novel idea implemented, efficiently identifies and adds new standard cells to the existing Static Standard Cell Libraries dynamically. This bridges the gap between two consecutive drive strength values for standard cell in the most optimal way.
  • Significant improvement in QOR (Area/Power/Timing reduction) is observed in synthesis stage of design.

 

Undergraduate Research
Design of Pulse Shapers for Read out Applications, DTU (January’12 – June’12)

Mentor: Dr. Neeta Pandey, Associate Professor, Department of Electronics and Communication Engineering, Delhi Technological University.

  • Simulation of Read Out Applications using CDTA and DDCCTA blocks in Orcad PSpice.
  • Designed highly efficient pulse shapers for detector readout front ends.
Design of Versatile Modulators and Frequency Agile Filters for AFE Designs, DTU (Jan’12 – June’13)

Mentor: Dr. Neeta Pandey, Associate Professor, Department of Electronics and Communication Engineering, Delhi Technological University.

  • Simulation of Versatile Modulator using CDTA and DVCCTA blocks in Orcad PSpice.
  • Designed highly efficient modulator scheme which can be used to implement AM,FM, Delta and Sigma-Delta modulation.
 Development of Highly Efficient Grid Connected Single Phase Rooftop PV System – Patentable Microinverter Topology and Control Scheme (July’12 – June’13)

Mentor: Prof. Vishal Verma, Professor, Department of Electrical Engineering, Delhi Technological University.

  • Designing and Hardware implementation of Single Phase Cascaded H-bridge Multilevel Microinverter for PV Rooftop Application with unique control scheme (patentable) and architecture for Photovoltaic panels..
  • Proposed and Implemented a unique algorithm for Global Maximum Power Point Tracking (GMPPT) for PhotVoltaic Power Systems under partial shading conditions.
Economic Load Scheduling of PV Standalone Systems, Indian Institute of Technology, Delhi (December’11) 

Mentor: Prof. Sukumar Mishra, Professor, Electrical Engineering Department, Indian Institute of Technology Delhi.

  • Economic Load Scheduling of PV Standalone Systems using Dynamic Programming and Rule Based Approach.
Implementation of MPPT Techniques, Photovoltaics, Indian Institute of Technology, Delhi (June’11-July’11)

Mentor: Prof. Sukumar Mishra, Professor, Electrical Engineering Department, Indian Institute of Technology Delhi.

  • Proposed, Designed and Implemented 17 Maximum Power Point Tracking for Photo Voltaic Power Systems (MPPT) Algorithms in MATLAB.
  • Worked on Fuzzy Logic, Neural Networks along with basic coding techniques for implementing the algorithms.
Simulation of Automated Industrial Applications using Programmable Logic Control, DTU (March’12 – May’12)

Mentor: Prof. Madhusudan Singh, Professor & Head of Department, Department of Electrical Engineering, Delhi Technological University.

  • Simulation of Automated Industrial Applications using PLC, LogixPro Simulator, Allen Bradley.
Designing of an Optical Mouse, DTU (January’11 – February’11)

Collaborator: Ishaan Malhotra, Software Engineer, Cisco Networks.

  • Designed Hand Gestures controlled optical Mouse using Image Processing techniques in MATLAB.