Industrial Experience

Engineer, Google LLC, Sunnyvale, CA (June’20 – Present)
  • Part of Hardware Platforms (Chip Implementation and Infrastructure-CI2) team.
Internship, Google LLC, Sunnyvale, CA (May’19 – August’19)
  • Part of Hardware Platforms team.
  • Proposed and developed FAIR (Fast, Accurate, Reliable and Insightful) average power estimation methodology for long-running arbitrary system-level workloads running on data center accelerators.
  • Achieved ≤ 5% estimation error at 99.90% confidence level on real workloads by analyzing less than 2% of workload state snapshot.
  • Filed IDF on the novel aspects of this work.
Internship, Apple Inc., Cupertino, CA (June’16 – August’16)
  • Part of SEG Custom CAD team.
  • Developed, enabled and deployed clock tree simulation methodology for cutting edge design nodes and different design types.
  • Developed SIGEM test case creation utility for net/port; validated XPS version for margin accuracy, power, leakage and runtime.
Engineer, Qualcomm India Pvt. Ltd., Bangalore (July’13 – July’15)
  • Worked as a Physical Design (PD) CAD Engineer, Qualcomm Bangalore Design Center, INDIA.
  • Physical design enablement, execution and timing methodology development on 20/28 nm nodes.
  • Development and deployment of Physical Design flows and Quality Assurance checker tools.
  • Automation and methodology development for PD flows/tools – PrimeTime, CLP, FV, ICC.
  • Physical Design CAD support (timing closure, PNR and Low power issues).
  • Collaborated with Standard Cell IP and Cores team for following cross-functional research projects:
    • Developed Dynamic Standard Cell Library Generation/Analyzer tool.  Improvement in area metrics by  1.590%, power reduction by 4.545% and frequency improvement by 8.5% at SoC level
    • Designed Versatile Modulator-Filter topology for Analog Front End (AFE) design. Filed IDF for patent app.
Internship, Qualcomm India Pvt. Ltd., Bangalore (June’12 – July’12)
  • Part of PD-CAD Team – Worked on CTS Enhancements of ELAN 28nm.
  • Clock Tree Synthesis, ASIC Design flow, VLSI Basics – Perl Scripting.
  • Static Timing Analysis (STA), Physical Design – Prime Time, ICC, Talus.
Project at Power Grid Corporation of India, Ltd., Gurgaon (April’12 - March’13)
  • Designed Economic Load Controller for Grid Connected Renewables (PV, Wind) Systems.
  • Simulated Rooftop PV Systems by designing of GMPPT Controller and DC-AC converters.
  • Done Literature Survey on Reactive Power Compensation Techniques for Wind Farms.
Student Lead, Image Processing Department, Hitech Robotics Systems, Delhi (June’11 – December’11)
  • Implemented various Image Processing operations for object recognition/obstacle detection and various methods of Real-Time Tracking (Optical flow, Contour extraction, Kalman filter etc.) in Visual C++.
  • Worked on camera calibration and angle detection techniques.
Internship, Power Grid Corporation of India, Ltd., Gurgaon (December’10)
  • Studied concepts related to ULDC Scheme, Communication Techniques, Smart Grid, Synchrophasors, SCADA and EMS.
  • Proposed installation locations of Syncrophasors based on Power Distribution Scenario in India.
Internship, Guru Hargobind Thermal Power Plant, Bathinda (August’10)
  • Working of a Thermal Power Plant.
  • Transmission at Substation.
  • Architecture of Distributed Control Systems.